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Cache of SIS :: 2005-2006: Spring :: 0618 Computer Engineering TechnologyJump to Course: [ 200 | 300 | 400 | 500 ]
| Course ID | Course Name |
Prof. | Size | Times |
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0618-503-01 |
Verilog Design II |
Lillie | 0/1 |
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0618-561-41 |
Embedded Sys Design I |
Lillie | 0/1 |
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0618-561-70 |
Embedded Sys Design I |
Lillie | 0/1 |
| T: 6:00pm-7:30pm | 13 1340 | | R: 6:00pm-7:30pm | 13 1340 |
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0618-561-85 |
Embedded Sys Design I |
Lillie | 0/1 |
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0618-562-01 |
Embedded Sys Design II |
Zion | 0/1 |
| M: 4:00pm-5:30pm | 09 3149 | | W: 4:00pm-5:30pm | 09 3149 |
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0618-562-85 |
Embedded Sys Design II |
Zion | 0/1 |
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0618-563-01 |
Embedded Sys Design III |
Eastman | 0/1 |
| M: 9:00am-10:00am | 70 1435 | | W: 9:00am-10:00am | 70 1435 | | F: 9:00am-10:00am | 70 1435 |
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0618-563-41 |
Embedded Sys Design III |
Eastman | 0/1 |
| W: 10:00am-12:00pm | 70 1360 |
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0618-563-42 |
Embedded Sys Design III |
Eastman | 0/1 |
| M: 12:00am-12:30am | Interpreter | | T: 12:00am-12:30am | Interpreter | | W: 2:00pm-4:00pm | 70 1360 | | W: 12:00am-12:30am | Interpreter | | R: 12:00am-12:30am | Interpreter | | F: 12:00am-12:30am | Interpreter | | S: 12:00am-12:30am | Interpreter |
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